The present invention is directed in general toward apparatus and method for performing signal processing functions and, more particularly, toward apparatus and method programmable to perform a variety of signal processing functions.
There is an ever increasing need to perform a multiplicity of digital signal processing functions, e.g. finite impulse response filtering, infinite impulse response filtering, convolution, correlation, etc. These functions are characterized by the need to perform a plurality of identical subfunctions on a sequence of digital data wherein each function is a unique combination of these identical subfunctions. For example, to implement an nth order finite impulse response filter, where the filtered result y is equal to a summation of the products of a series of digital data input, one must implement the equation: EQU y.sub.k =a.sub.o x.sub.k +a.sub.1 x.sub.k-1 +a.sub.2 x.sub.k-2 + . . . +a.sub.n x.sub.k-n.
The expression comprises a serial combination of subfunctions wherein the subfunction comprises one multiplication and one addition.
With the continuing application of digital signal processing functions to physical devices, such as image reconstruction, these functions are required to be performed at higher and higher rates of speed. The present invention provides apparatus and method for implementing such functions in a manner such that a series of concurrent multiplications and additions can be performed to provide a sequence of filtered data output.
Prior art systems for processing digital information have relied primarily upon a central processing unit coupled to a plurality of digital data storage elements for performing a plurality of sequential digital operations upon digital data under program control. Many of these operations involve multiple transfers of digital data to and from memory in addition to performing the necessary arithmetic operations.
For example, to perform a finite impulse response filtering, like that described above, a traditional data processing device would be required to: retrieve a.sub.0 x.sub.k from their respective memory locations; multiply a.sub.0 and x.sub.k to form a first product; store this product in a partial sum memory location; retrieve a.sub.1 and x.sub.k-1 from their respective memory locations; multiply a.sub.1 and x.sub.k-1 to form a second product; retrieve the partial sum from its memory location; add the partial sum to the second product to form a new partial sum; and store the new partial sum in the partial sum memory location etc., until each of the n operands have been multiplied and summed. Such operations require complex programming and, more importantly, are extremely time-consuming.
Newer devices for performing digital signal processing functions provide apparatus for performing successive operations, however, such devices do not allow for programmability and therefore are highly function specific. One such device is shown and described in U.S. Pat. No. 4,142,242 to Duvochel et al. (1979).
It is desirable, therefore, to provide apparatus to perform a variety of digital signal processing functions. It is also desirable to provide apparatus to perform digital signal processing functions without the need to continuously store and retrieve data from memory. It is also desirable to provide apparatus to perform rapid digital signal processing functions on a series of input data to provide a series of output data.